Linear regulators form an integral part of the power supply scheme for a phase locked loop (PLL). The regulator, while acting as a stable voltage source that supplies current, also shields the PLL from noisy supply fluctuations that can directly translate to jitter, leading to deterioration in its performance. Low supply voltages and tight jitter constraints necessitate the use of low dropout (LDO) regulator topologies that provide a high PSRR.
PLLs act as high pass filters, rejecting power supply noise only for frequencies less than the BW/10, where BW is the bandwidth. At higher frequencies, it is the function of the regulator to provide PSRR.
Most LDO topologies use a PMOS series pass device at the output. This increases the resistance of the output stage (over that of an output stage using an NMOS pass device) and necessitates the use of a large off-chip capacitor to compensate the circuit. This capacitor also provides a high power supply ripple rejection (PSRR) for the regulator. The value of this capacitor is often prohibitive for on-chip fabrication.
Any solution to compensate the circuit forming the dominant pole at the output of the amplifier (first stage), Miller compensation, for example, would yield a low PSRR at high frequencies since the load capacitor would have to be small to provide stability over operating conditions.
Prior art solutions for achieving a high power supply rejection ratio (PSRR) for a low dropout regulator (LDO) include: (1) using a large off-chip capacitor for compensation and high PSRR and (2) using nested miller compensated circuits. For the prior art solutions mentioned above, off-chip capacitors are not feasible for monolithic solutions. Further, the compensation of nested-miller-compensation circuits is complicated and they may not yield a good PSRR at high frequencies without off-chip capacitors.